Design methodologies and VLSI architectures for cyber security hardware accelerators

The research presented in this Thesis focuses on efficient implementation of cryptographic hardware accelerators developed in the European Processor Initiative (EPI) framework. EPI is a project under development with the aim of implementing the first processor fully designed in Europe intended to be used in high performance applications such as Big-Data analysis. To ensure an appropriate level of security, the EPI processor embeds several dedicated sub-systems to manage the cybersecurity aspects. Each of these sub-systems is based on a suite of cryptographic hardware accelerators denoted Crypto-Tile. The Crypto-Tile is composed by four different cryptographic co-processors, each of them provides hardware acceleration for a specific algorithm or service: Advanced Encryption Standard (AES) for symmetric key data encryption, Secure Hash Algorithm (SHA) for message digest computation, hardware-based Random Number Generator (RNG) and Elliptic Curve Cryptography (ECC) support for asymmetric key data encryption and digital signature. Furthermore, the Crypto-Tile provides advanced security features such as internal storage of cipher keys, configurable policies for accesses control and clock randomization to provide a preliminary countermeasure against timebased and statistical attacks. The research activity addresses the hardware optimization of the implemented cryptographic accelerators. The work was mainly focused on the Crypto-Tile implementation that respects the system requirements with the best trade-off between performance and logic resources usage. In particular, an extensively design investigation has been performed to reduce the system logic complexity exploiting shared logic inside the cryptographic engines, as in the case of AES core that reuses the same combinational logic to perform several block cipher modes. The Crypto-Tile has been synthesised using a 7 nm standard-cell technology, providing a new characterization on this extremely scaled technology of the implemented cryptographic accelerators respect to the state-of-the-art.