Wire delay effects reduction techniques and topology optimization in NUCA based CMP systems

One of the most important issues designing large last level cache in a CMP system is the increasing effect of wire delay problem which affects the banks access time and reduces the performances. Some CMP systems adopt a shared L2 cache to maximize cache capacity, instead other architectures use private L2 caches, replicating data to limit the delay from slow on-chip wires and minimize cache access time. Ideally, to improve performance for a wide variety of workloads, CMPs prefer both the capacity of a shared cache and the access latency of private caches. In this context, NUCA caches have been proved to be able to tolerate wire delay effects while maintaining a huge on-chip storage capacity. In this thesis we analyze the influence on system's behaviour of different coherence protocols (MESI and MOESI) and the effect of topology changes as design tradeoffs for S-NUCA based CMP system. Our results show that CMP topology has a great influence on performances, instead, in this scenario, the protocol has not. Then we propose and evaluate a novel block migration scheme to reduce access latency in a shared cache for D-NUCA based systems, in which are addressed two specific problems that can arise due to the presence of multiple traffic sources. Finally, we present a power consumption model we used to evaluate the energy behaviour of both static and dynamic NUCA systems. We observe the most important element of power consumption is always the static component, but the influence of the dynamic onsumption is increasing.