Optimizing Quantum Circuit Layout using Quantum Annealing

Quantum computing has garnered significant interest due to its theoretical potential for exponential speedup in computations. This advantage arises from the unique properties of quantum mechanics, which enable quantum bits (qubits) to exist in multiple states simultaneously and to become entangled. However, the current Noisy Intermediate-Scale Quantum Computing era is constrained by the limited number of available qubits and their high sensitivity to environmental noise. In this thesis, we consider a quantum circuit-based model, recognized for its universality in encoding any computation. Nevertheless, leveraging this model requires adherence to the constraints imposed by quantum hardware. One critical limitation is the Nearest Neighbor condition, prevalent in quantum hardware architectures, which necessitates that computations should be performed solely on adjacent qubits. Consequently, additional swapping operations, or SWAP gates, are required to make interacting qubits neighboring. Given the high computational cost associated with these SWAP gates, it is essential to minimize their usage. To address this challenge, we introduce two hybrid quantum-quantum approaches designed to adapt quantum circuits for the Noisy Intermediate-Scale Quantum era by utilizing quantum computing technologies. Both approaches are based on the qubit line reordering technique and use Quantum Annealing in the optimization part. The first approach optimizes a quantum circuit by global qubit line reordering based on the Graph Partitioning problem formulation. The second approach implements local qubit line reordering using Boolean satisfiability theory. As our problem-solving tool, we use Quantum Annealing, leveraging its capabilities as a quantum heuristic optimization solver. Our numerical experiments, conducted with several benchmark quantum circuits, demonstrate promising results in optimizing the circuits.