In this work the investigation on fully integrated systems providing on-chip galvanic isolation is presented, which exploits a silicon technology by STMicroelectronics. This research is mainly motivated by the higher level of integration that is demanded to the next generation of power converters and general applications featuring galvanic isolation. State-of the art implementations rely on complex post-processed passive devices to implement isolated power transfer within multi-die system in packages. In this work, two silicon implementations are mainly discussed, i.e. a step-up power transfer system and the ASK data receivers of a data/power transfer system. They achieve up to 980 mW output power with 29.6% efficiency and up to 40 Mbps with 5% modulation index, respectively, thus showing enhanced performance with respect to the state-of-the-art. Each system requires only two silicon chips to implement both galvanic isolation and power transfer, thus achieving the highest possible level of integration for a pure silicon technology.
Fully integrated systems with on-chip galvanic isolation in silicon technology
2015
Abstract
In this work the investigation on fully integrated systems providing on-chip galvanic isolation is presented, which exploits a silicon technology by STMicroelectronics. This research is mainly motivated by the higher level of integration that is demanded to the next generation of power converters and general applications featuring galvanic isolation. State-of the art implementations rely on complex post-processed passive devices to implement isolated power transfer within multi-die system in packages. In this work, two silicon implementations are mainly discussed, i.e. a step-up power transfer system and the ASK data receivers of a data/power transfer system. They achieve up to 980 mW output power with 29.6% efficiency and up to 40 Mbps with 5% modulation index, respectively, thus showing enhanced performance with respect to the state-of-the-art. Each system requires only two silicon chips to implement both galvanic isolation and power transfer, thus achieving the highest possible level of integration for a pure silicon technology.I documenti in UNITESI sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/20.500.14242/232870
URN:NBN:IT:UNICT-232870