A Structured Approach to Stream Processing on Reconfigurable Hardware

Continuous data streams are now central in domains such as industrial monitoring, finance, and the Internet of Things. Unlike batch workloads, they must be processed in real time to extract timely insights. The Stream Processing paradigm enables this, but achieving high throughput and low latency often requires specialized hardware. Current Stream Processing Engines (SPE), however, are mainly designed for distributed clusters and struggle to exploit single-node systems with accelerators. Among available accelerators, Field Programmable Gate Arrays (FPGAs) stand out for their efficiency and performance. Yet their adoption is limited because FPGA programming relies on complex toolchains and hardware expertise, making them difficult to use in practice. This thesis demonstrates that these limitations can be overcome by introducing higher-level abstractions for FPGA programming. A High-Level Language (HLL) is proposed that lets developers describe applications in terms of operators, routing, and state management without hardware-specific details. These descriptions are compiled into modular Building Blocks (BBs), which are then mapped to optimized implementations across FPGA platforms. The research introduces a structured methodology, two complementary implementation strategies (code generation and code library), and host APIs that simplifies data transfers and runtime coordination. Experiments on synthetic and real-world benchmarks show that the proposed frameworks deliver high throughput and low latency while reducing development complexity. By integrating seamlessly with existing SPEs, this work makes FPGA acceleration practical and accessible, supporting its broader adoption in data-intensive domains.