High Voltage Biasing Circuits for Sensor Interfaces Built in 55nm CMOS

Microelectromechanical systems (MEMS) are silicon-integrated devices fabricated with conventional IC processes that incorporate moving mechanical structures. They are well suited to sensing applications. Among MEMS sensors, microphones have gained strong market traction because the transducer can be co-integrated with the readout and biasing ASIC on the same substrate and housed in a single package, reducing production cost and improving area efficiency versus prior technologies. To meet the stringent size constraints of portable systems, scaling of digital circuitry must be matched by comparable scaling of analog blocks. Operating analog functions in advanced, low-voltage nodes introduces challenges in maintaining performance at low power while meeting or exceeding figures achieved in larger, higher-power technologies. While many state-of-the-art MEMS readout and biasing ASICs target CMOS nodes from 180 nm to 65 nm, this work demonstrates feasibility in a standard 55 nm process, leveraging gains in area efficiency and power reduction. A typical sensor-biasing chain includes several elements, with the high voltage charge pump (CP) being among the most critical. Implemented as an inductorless DC–DC converter, the CP multiplies a reference voltage to generate the high bias required by the sensor. In MEMS microphones, this bias may reach tens of volts because sensitivity — and therefore SNR — scales with the bias level. This thesis presents a high-gain, programmable CP system with an on chip clock generator for MEMS microphone biasing. The CP employs an innovative bootstrapped switching structure that limits device-level voltage stress to within the supply rail, avoiding dedicated high-voltage transistors. The output is trimmed from 4.6 V to 18.3 V in uniform 200 mdBV steps by adjusting the CP input via an OTA closed around a digitally programmable resistive divider; the divider is designed so the regulated voltage becomes an exponential function of a 6-bit trimming code. The CP clock is generated on-chip by a low-voltage, low-power relaxation oscillator (RxO) that relies on a threshold-based current reference and a matched single-transistor comparator. The comparator requires no external reference, being implicitly referenced to its own threshold, and the reference provides robust biasing under reduced headroom. The proposed system achieves a maximum output voltage of 18 V while drawing 2.6 µW from a 1.2 V supply and occupying 0.06 mm² of active silicon. Measured and post-layout validated results demonstrate that the industrial targets set for the project have been met. The developed blocks provide a solid foundation for future product-grade implementations and can be adapted to similar system requirements with minimal process overhead and high integrability.