Bandgap reference and Low Dropout Regulators (LDOs) for sensors and IoT systems in deep sub-micron CMOS technologies

Low-power and battery-operated sensors and IoT systems demand accurate and low noise voltage and current references, as well as ripple-free supply lines, to deliver their performances. As production costs, area and power become more and more critical, technology is advancing toward deep sub-micron CMOS nodes. This makes reliable biasing increasingly challenging, requiring new innovative solutions to deliver performance. This PhD thesis introduces a current mode Bandgap reference (BG) in 55nm CMOS, embedding a higher order curvature correction circuit which enhances the BG precision over temperature, limits critical Process Voltage and Temperature (PVT) variations, and lowers the BG current consumption. Moreover, a high gain error amplifier is implemented adopting a cascode structure to increase the gain and address the limited MOSFET output impedance, all without an additional current burden. Despite the inherent challenges of 55nm nodes, including lower intrinsic gain, significant parasitic coupling, and volatile technology parameters, the circuit demonstrates robust performance. In particular, a temperature coefficient of just 5.06 ppm/°C across a temperature range of −40 °C to 100 °C, line regulation of 0.011 mV/V, and a power supply rejection ratio (PSRR) of −81.5 dB were measured. These results were achieved while operating at a nominal 1.2 V supply voltage and drawing only 4.85 μA. Additionally, a folded Flipped-Voltage-Follower (FVF) based LDO is presented. The output FVF stage features a wide bandwidth local loop to manage fast load transients and efficiently drive the load capacitor. In particular, a folded FVF topology is designed to ensure proper biasing across all supply voltages and boost the loop gain, critical in deep sub-micron technologies. Dynamic compensation and adaptive biasing have been incorporated to maintain stability at any load current, overcoming technology and process, voltage, and temperature (PVT) challenges while leveraging the excellent matching characteristics of the circuit. The fast FVF loop is coupled with second high gain Error Amplifier-based loop which operates at a lower bandwidth. This second loop guarantees excellent low frequency performances and load regulation. Therefore, the limitations of the 55nm CMOS technology are effectively addressed by splitting the LDO tasks between the two complementary feedback loops. Furthermore, two Power Supply Rejection Ratio (PSRR) enhancement techniques are proposed to improve the standard folded FVF LDOs PSRR: ac-only bulk biasing and a feed-forward ripple injection circuit. In fact, conventional methods, such as increasing loops bandwidth and gain, offer only limited PSRR improvements in deep sub-micron technology, especially within the constraints posed by low area and restricted current budgets typical of battery-powered sensors and IoT applications. Therefore, the proposed techniques target the PSRR direct transmission path of supply rail disturbances to the LDO output with no influence on the other LDO performances. Measures LDO results demonstrate PSRR improvements up to 17 dB and 22 dB respectively with just 1.5 μA extra current and a negligible silicon area increase. Among the LDOs, the best measured results in 55nm CMOS include a total current consumption of 6.4 μA, a PSRR of −50.4 dB at 1 MHz, line and load regulation of 11 μV/V and 13 μV/mA, and a settling time of 150 ns. Moreover, the proposed LDOs can operate with a current efficiency up to 98.9% and under a supply voltage ranging from 1.08 V to 1.8 V, yielding a minimum dropout voltage of only 80 mV.