The work presented in this thesis is focused on the design of a 32 channel CMOS front-end ASIC intended for the read-out of GEM detectors to be used in a new proton-therapy facility for beam monitoring. Each single analog channel, based on the classic architecture CSA + shaper, is able to sample the energy of the incoming event by means of a peak detector (PD) which works as an analog memory during the read-out phase. In order to have energy information directly in digital form, the ASIC is equipped with an integrated 8-bit subranging ADC, so the outputs of the PDs are multiplexed towards the A/D conversion path. The outputs of 32 voltage discriminators, which compare the shaper outputs with a programmable threshold, produce an accurate and fast trigger signal which identifies with good time resolution the occurrence of a valid event. The read-out of the channels, the A/D conversion and the configuration of the ASIC are managed by a digital part which also carries out data serialization on a 100 Mbit/s LVDS serial link. Measured results are presented, showing the full functionality of the ASIC and the performance of the analog channel in good agreement with the given specification.

Front-end Electronics for GEM detectors

Ciciriello, Fabio
2017

Abstract

The work presented in this thesis is focused on the design of a 32 channel CMOS front-end ASIC intended for the read-out of GEM detectors to be used in a new proton-therapy facility for beam monitoring. Each single analog channel, based on the classic architecture CSA + shaper, is able to sample the energy of the incoming event by means of a peak detector (PD) which works as an analog memory during the read-out phase. In order to have energy information directly in digital form, the ASIC is equipped with an integrated 8-bit subranging ADC, so the outputs of the PDs are multiplexed towards the A/D conversion path. The outputs of 32 voltage discriminators, which compare the shaper outputs with a programmable threshold, produce an accurate and fast trigger signal which identifies with good time resolution the occurrence of a valid event. The read-out of the channels, the A/D conversion and the configuration of the ASIC are managed by a digital part which also carries out data serialization on a 100 Mbit/s LVDS serial link. Measured results are presented, showing the full functionality of the ASIC and the performance of the analog channel in good agreement with the given specification.
2017
Italiano
Corsi, Francesco
Marzocca, Cristoforo
Passaro, Vittorio
Politecnico di Bari
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14242/63971
Il codice NBN di questa tesi è URN:NBN:IT:POLIBA-63971