Design of a revised DDS-PLL phase shifter architecture for phased arrays

The growing interest towards electronically scanning arrays, both in warfare applications (e.g. synthetic aperture radars) and in consumer electronics (e.g. wireless communications), has resulted in an extensive research towards Beam Steering Units (BSUs) capable of implementing fine-grained phase shifts at each of their antennas. The scope of this phase reconfiguration is to conveniently focus and steer the radiation pattern of the phased array, and thus obtain a behavior that is not achievable through single element antennas. Among the many state of the art solutions that can be used to implement BSUs for phased arrays, Direct Digital Synthesizer-based Phase Locked Loop (DDS-PLL) phase shifters seem the most promising due to their frequency independent theory of operation. DDS-PLLs are circuit solutions capable to synthesize, with an exceptional phase resolution, phase shifted Local Oscillators (LOs) in the GHz range from conveniently delayed low-frequency signals. The purpose of this thesis is to present my attempt to decrease the complexity of DDS-PLL phase shifters through the design of an all-digital Phase Control Unit (PCU) that supersedes the need for complete DDS ICs in DDS-PLLs (being the DDS-DAC block the most important contributor to their power consumption). Since in modern PLLs the phase and frequency mismatch detection are operated by converting the reference signal into a square wave, the proposed PCU gets rid of the unnecessary digital-to-analog transformation that takes place into the DDS IC. The PCU architecture has been described in VHDL and compiled for FPGA. It is made up of chains of shift registers with programmable lengths, a.k.a. Synchronous Delay Lines (SDLs). In the discussed prototype, the PCU is made up of 4 chains of shift registers (one per each antenna of the phased array), outputting 1-MHz square waves whose phase can be independently adjusted in 256 steps (namely with an 8-bit resolution) in the [0°; 360°] range. A complete FPGA-based BSU prototype has been implemented. This has been done through the integration of an open-source microcontroller IP-core into the FPGA design and the fabrication of a custom Printed Circuit Board (PCB) housing the PLLs. This prototype synthesizes 4 LOs centered at 2.453-GHz and maintains the same phase resolution of the PCU, thanks to a developed technique based on the theory of operation of DDS-PLLs. A beam steering transmitter has also been implemented. This has been done through the fabrication of a linear array of patch antennas and a frequency up-conversion PCB. The transmitter has been used to evaluate a steerable WCDMA wireless link centered at 3.350-GHz.