Towards the heterogeneous, real-time reconfigurable embedded system

To improve the computing performance in real-time applications, modern embedded platforms comprise hardware accelerators that speed up the tasks’ most computeintensive parts. A recent trend in the design of real-time embedded systems is to integrate field-programmable gate arrays (FPGA) that are reconfigured with different accelerators at runtime, to cope with dynamic workloads that are subject to timing constraints, like in signal processing or computer vision applications. One of the major limitations when dealing with partial FPGA reconfiguration in realtime systems is that the reconfiguration port can only perform one reconfiguration at a time: if a high-priority task issues a reconfiguration request while the reconfiguration port is already occupied by a lower-priority task, the high-priority task has to wait until the current reconfiguration is completed (a phenomenon known as priority inversion), unless the current reconfiguration is aborted (introducing unbounded delays in lowpriority tasks, a phenomenon known as starvation). Moreover, hardware accelerators reconfigured at runtime inside the FPGA usually require minimum interaction with the software side and perform massive computations on data which have to be read from the main memory or written to it. Therefore, In case of high-throughput hardware accelerators may happen that the communication medium shared between main memory and hardware and software sides is not able to accept more requests jeopardizing the functioning of the whole system. Furthermore, as the software can not control each bus transaction of an hardware accelerator, mis-designed accelerators could perform illegal memory accesses corrupting the main memory. This thesis shows how priority inversion and starvation can be solved by making the reconfiguration process preemptive, i.e., allowing it to be interrupted at any time and resumed at a later time without restarting it from scratch. Such a feature is crucial for the design of runtime reconfigurable real-time systems, but not yet available in today’s platforms. Furthermore, the trade-off of achieving a guaranteed bound on the reconfiguration delay for low-priority tasks and the maximum delay induced for high-priority tasks when preempting an ongoing reconfiguration has been identified and analyzed. Besides, this work addresses the problems of memory protection and bus predictability by showing a solution to prevent hardware accelerators from choking the communication bus or performing illegal memory accesses, making the communication more predictable and allowing for more precise analysis. A custom memory protection and budgeting unit (MPBU) has been developed for this purpose. Experimental evaluation on the Xilinx Zynq-7000 platform have been realized for preemptive reconfiguration and MPBU. Results show that the proposed implementation of preemptive reconfiguration introduces a low runtime overhead, thus effectively solving priority inversion and starvation. Moreover, experimental results show that memory corruption and bus chocking problems can be avoided and the communication over a shared bus can be made more predictable allowing to have less stringent timing constraints in the analysis.