Direct Model Predictive Control of Inverter Cascaded H-Bridge

Model predictive control (MPC) has gained increasing attention in the last decades in the power electronics field. Among the different versions of MPC, the most popular one is the so-called finite control set MPC (FCS-MPC or direct MPC), which does not require a modulation algorithm and is characterized by a fast dynamic performance. However, it suffers from high computational cost when applied to multilevel converters, and it requires a large amount of calculations that grows when the number of levels increases, which affects the practical real-time implementation and performance. This thesis addresses the challenge of reducing the computational burden of the FSC-MPC for cascaded H-bridge (CHB) multilevel inverters. Neural networks were investigated to significantly speed up the computation of the control law while guaranteeing satisfactory performance. An analytical solution was also developed to dramatically decrease the number of calculations needed to compute the optimal control. A CHB static synchronous compensator (CHB-STATCOM) was employed as a test bench for the presented studies. Theoretical discussions of the proposed methodologies are provided and comparisons among them and existing methods are given, underlying that the presented methods overcome the state-of-the-art approaches. The proposed solutions were analyzed in a simulation environment by using Matlab/Simulink, through hardware in the loop and, finally, implemented on a 5-level CHB-STATCOM prototype. The control techniques were fully implemented on FPGA, while the digital signal processors on the individual H-bridges were programmed to sample voltages and currents. The thesis describes the firmware implementation and the most critical encountered problems and the related solutions are discussed. Specifically, the use of current transformer sensors to sense the three-phase currents was the cause of a DC offset in the output currents. A software solution was developed to solve this problem by adding an MPC optimization problem to the overall algorithm. Practical issues of the serial peripheral interface protocol for transferring the measurements to the master FPGA are presented and a solution for minimizing the communication delays is presented.