Oscillator Design for D-Band Wireless Communication Applications

This manuscript presents a dual-core oscillator with third-harmonic extraction at 150GHz. The oscillator is built around a Colpitts topology, leveraging the harmonic-rich transistor drain current for its extraction. The addition of a transformer-based resonator boosts the loop gain, allowing for a reduction of the transistor size and parasitics while peaking the impedance at the third harmonic of the fundamental oscillation frequency. Small- and large-signal circuit analyses are presented in this paper to derive guidelines for design optimization. Two oscillator cores are also coupled for 3dB phase noise improvement. Magnetic coupling in the resonators is exploited for coupling, leading to a simple layout without extra parasitic elements and good robustness to mismatches. A test chip is designed and fabricated in Global Foundries 22nm CMOS FDSOI technology. The fundamental oscillation frequency is tunable from 47.5GHz to 51.5GHz, and the third harmonic is extracted from 142.5GHz to 154.5GHz. With 25.6mW from 0.8V voltage supply, the measured phase noise at 1MHz offset at 154.5 GHz is -87.4dBc/Hz, corresponding to -177.1dBc/Hz Figure-of-Merit (FoM). To the best of the authors' knowledge, this work demonstrates the lowest phase noise and the best FoM among reported CMOS oscillators delivering a signal in the same frequency range.