A design and verification methodology for networked embedded systems

Nowadays, Networked Embedded Systems (NES’s) are a pervasive technology. Their use ranges from communication, to home automation, to safety critical fields. Their increasing complexity requires new methodologies for efficient design and verification phases. This work presents a generic design flow for NES’s, supported by the implementation of tools for its application. The design flow exploits the SystemC language, and considers the network as a design space dimension. Some extensions to the base methodology have been performed to consider the presence of a middleware as well as dependability requirements. Translation tools have been implemented to allow the adoption of the proposed methodology with designs written in other HW description languages.