The aim of this thesis is to provide efficient methodologies to improve ABV in three domains of generation, abstraction and qualification of PSL assertions. The main contributions of this thesis can be summarized as follows: 1- An automatic mining methodology has been proposed, for capturing behavioral descriptions of a system that can generate set of temporal assertions from execution traces. The approach is particularly suited for mining assertions that describes arithmetic relations between inputs and outputs according to a set of temporal patterns. In comparation with state of the art, assertion miner proposed in this methodology, generates a set of more compact and higher quality assertions. 2- An automatic abstraction methodology has been proposed to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. The methodology can be divided into two main phases, firstly, assertions synthesized into C++ methods and secondly, inserted in the TLM model. The results show that the methodology can abstract and reuse assertions from RTL to TLM and avoid redefinition of assertions which are already exist at RTL. 3- An automatic qualification methodology has been proposed to evaluate the quality of assertions to measure the interestingness of assertions. The approach re-adapts metrics from data mining to measure the quality of assertions based on its activation frequency during simulation runs and the correlation between antecedent and consequent. Experimental result depicts the proposed methodology provides a better estimation of assertions interestingness.

Improving ABV by generation and abstraction of PSL assertions

GHASEMPOURI, TARA
2016

Abstract

The aim of this thesis is to provide efficient methodologies to improve ABV in three domains of generation, abstraction and qualification of PSL assertions. The main contributions of this thesis can be summarized as follows: 1- An automatic mining methodology has been proposed, for capturing behavioral descriptions of a system that can generate set of temporal assertions from execution traces. The approach is particularly suited for mining assertions that describes arithmetic relations between inputs and outputs according to a set of temporal patterns. In comparation with state of the art, assertion miner proposed in this methodology, generates a set of more compact and higher quality assertions. 2- An automatic abstraction methodology has been proposed to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. The methodology can be divided into two main phases, firstly, assertions synthesized into C++ methods and secondly, inserted in the TLM model. The results show that the methodology can abstract and reuse assertions from RTL to TLM and avoid redefinition of assertions which are already exist at RTL. 3- An automatic qualification methodology has been proposed to evaluate the quality of assertions to measure the interestingness of assertions. The approach re-adapts metrics from data mining to measure the quality of assertions based on its activation frequency during simulation runs and the correlation between antecedent and consequent. Experimental result depicts the proposed methodology provides a better estimation of assertions interestingness.
2016
Inglese
Verification, Embedded system, Assertion generation, Assertion abstraction, Assertion qualification, TLM, RTL, Data mining
95
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14242/181954
Il codice NBN di questa tesi è URN:NBN:IT:UNIVR-181954