Design and Verification Techniques for TLM-based Design Flows

Transaction-level modeling (TLM) is nowadays a promising design style to deal with the increasing complexity of modern embedded systems. A TLM-based flow involves different verification techniques according to the system being designed and the exhaustiveness of the results to be achieved. The design flow may involve a transition from or to a lower abstraction level (RTL), both for design and verification purposes. Refinement from TLM to RTL is performed to move closer to the physical realization of the system being designed. On the other hand, abstraction from RTL to TLM allows to reuse third-party or already developed components and to integrate them into a system-level design, thus gaining a reduction of design time and costs and an increase in simulation speed. Finally, a further refinement step consists of gate-level synthesis, which brings the design even closer to its physical realization. At this level, test generation is typically a time-consuming activity, so techniques can be adopted to reduce such computation times.