Development and analysis of circuit-level solutions for accurate high-speed SAR converters

Handling large flows of data is one of the main challenges of the modern world. High-performance computing infrastructures and telecommunication networks require data interfaces capable of high bit rates. Due to the inherent robustness of digital signal processing (DSP) techniques, high-speed data interfaces have been increasingly relying on digital elaboration to implement key functionalities such as demodulation and equalization. Clearly, these system depend on high-speed analog-to-digital converters (ADCs) to move signals to the digital domain. Over the last 15 years, successive approximation register (SAR) ADCs have become increasingly popular in a wide variety of applications thanks to their ability to take advantage of technological scaling. Through time interleaving, SAR converters are able to achieve the sampling rates required by the most advanced communication systems while maintaining remarkable power efficiency. Clearly, the performance of a time-interleaved (TI) ADC depends considerably on the characteristics of the single-channel converters that are part of it. A single-channel ADC for time interleaving applications should exhibit a good balance between speed and power consumption and target an effective resolution that is slightly above the specification of the system. In high-speed ADCs with medium-high resolutions (8-10 bit), increasing the sampling rate without compromising accuracy can represent a challenging task. For this reason, the investigation of techniques that relax the trade-off between sampling frequency and noise/distortion is a research field of great relevance. This thesis explores circuit-level solutions for improving the speed/accuracy trade-off in SAR converters, focusing on the optimization of the comparator and capacitive DAC (CDAC). In particular, the present manuscript introduces a novel CDAC switching scheme and three novel comparator topologies. The proposed switching scheme allows to adjust the trajectory of the output common-mode voltage of the CDAC in such a way to optimize comparator performance. The proposed comparators, on the other hand, achieve low delay with no penalties in terms of input-referred noise and offset. In addition, the three comparator topologies have been analyzed in order to provide a theoretical validation and to derive useful design guidelines for each of them. This manuscript also describes the design and characterization of ADC1 and ADC2, two high-speed SAR ADCs implemented in 55 nm CMOS in the context of a prototyping activity for the “Sustainable tecHnologies enablIng Future Telecom applications” (SHIFT) project. The development of the two converters also represented an opportunity for further validating the proposed CDAC switching scheme and one of the aforementioned comparator topologies. Post-layout simulation results highlight the effectiveness of the proposed approaches. ADC2, in particular, achieves a sampling rate of 200 MS/s and a signal to noise and distortion ratio (SNDR) of 57.5 dB while absorbing 2.37 mW from a 1 V supply. The resulting Walden figure of merit (FoM) is approximately 19 fJ/conv. step, which is close to the recent state of the art in the field of high-speed SAR ADCs. The two converters will be also characterized through measurements as soon as the prototypes are available.