Analysis and Mitigation of Memory Contention in Real-Time Embedded Systems

The thesis deals with the effect of memory interference on the WCET of tasks, its possible effects, and how hardware-based technologies can help to mitigate them. The discussion is divided into fourparts: the first deals with the memory interference generated by I/O devices and how hardware-based memory-bandwidth regulators can help to mitigate its effects on both CPU cores and other devices. The second part focuses on memory interference generated by CPU cores and the possibility of utilizing the ARMv8 MPAM extension in order to reduce it. The study begins with a deep analysis of the specifications that allow the creation of a real-time model of MPAM's mechanisms. These are exploited for the design of an optimization problem that can be used to compute the worst-case memory interference that can be guaranteed by MPAM's mechanisms. The third part presents an I/O virtualization framework supporting memory bandwidth regulation on the traffic produced by I/O devices. The fouth part deals instead with the possible effects of WCET overruns caused by interference. In particular, an analysis-based technique is developed in order to compute the minimum amount of extra interference needed to have a non-linear jump in the response-time bound of a task (computed through the response-time analysis). An optimization problem is finally built to exemplify possible real scenarios that could lead to such an increase in interference.