A SAR-assisted Incremental ΣΔ ADC with Accumulation based S/H Circuit for Shunt Current Measurements

Abstract: This thesis presents a SAR-assisted first-order incremental ΣΔ analog-to-digital converter (ADC) that features an accumulation-based sample- and-hold (S/H) circuit. The purpose of this circuit is to effectively mitigate the (kT/C) noise contribution, which can be a potential bottleneck for the resolution performance of the converter. The system has been designed for shunt current measurements in brushless DC motor (BLDCM) speed control. Accurate sensing and digitization of current information play a crucial role in effectively monitoring and regulating the behavior of the motors. The sensor digitizes the voltage drop across an external shunt resistor when current flows through it. Specifically, the sensor consists of an accumulation-based S/H circuit to handle a high common-mode voltage range of 0–60 V, followed by a successive approximation register (SAR)-assisted incremental delta-sigma ADC. The sensor was fabricated using a standard 0.13 μm CMOS process. It occupies an area of 0.4 mm² and draws 6.7 mA from a 1.5 V supply. Over the temperature range of -20°C to 100°C and a ±4 A current range, it achieves a gain error of ±0.8%. With this shunt configuration, it achieves a dynamic range of 78 dB in a 2.75 μs conversion time.