Design of Analog Circuits for Analog in Memory Computing based on Phase Change Memories

The execution of modern AI algorithms on standard Von-Neumann computing architectures implies movement of a huge amount of data between the Central Processing Unit (CPU) and the memory unit, which leads to high energy consumption and speed degradation (i.e., Von-Neumann Bottleneck). For this reason, solutions have been recently proposed that perform computation directly within memory (In-Memory Computing) in order to limit data transfer: this operation is referred to as hardware acceleration. In particular, Analog In-Memory Computing (AIMC) based on Non-Volatile Memories (NVMs) has emerged as a promising strategy to implement hardware acceleration of Deep Neural Networks (DNNs). Typically, these systems are crossbar Resistive Switching (RS) memory arrays where the memory cells are located at the intersection points between horizontal metal lines known as Word-Lines (WLs) and vertical metal lines known as Bit-Lines (BLs). This structure, together with Kirchoff’s and Ohm’s laws, are exploited to perform, in the analog domain, Matrix-Vector Multiplications (MVMs), which are the core operation in AI inference. Since MVMs are performed directly within memory and since they are carried out in the analog domain, AIMC systems potentially lead to much greater speed and efficiency with respect to standard Von-Neumann computing architectures. The metric commonly used to evaluate the performance of AIMC systems in terms of speed and efficiency is the TeraOPerations per second over Watt (TOPs/W). In this thesis, a 24 TOPs/W AIMC system based on a 28 nm Phase Change Memory (PCM) developed in cooperation with STMicroelectronics is presented. In particular, the thesis describes in detail the design of analog circuits involved both during the execution of MVMs and during memory writing operations. In this respect, more details are provided regarding the design of the WL Driver circuit and two voltage regulators. For each of these circuits, the target is to satisfy design constraints that ensure the correct operation of the system and the required performance in terms of TOPs/W and program throughput. Finally, measurements are shown to demonstrate the effectiveness and the validity of the presented system.