ALL Digital Clock Generator and PLL-Less Solution

This thesis presents an innovative design of a Fractional Output Divider (FoD) and its enhanced version, the All-Digital Fractional Output Divider (ADFOD). The FoD adopts an open-loop structure, eliminating the need for traditional Phase-Locked Loop (PLL) feedback control. Through digital techniques, it dynamically adjusts both integer and fractional division ratios, while precisely regulating phase interpolators to generate output clock frequencies ranging from 1 MHz to 300 MHz at a working frequency of 2.4 GHz. By incorporating sigma-delta modulation, the design effectively suppresses quantization noise, achieving high-precision, low-jitter clock signals. Building upon the FoD, the ADFOD introduces phase compensation, digitally controlled frequency generation, and phase interpolation to further enhance performance. The ADFOD dynamically measures the period of the free-running oscillator, combining it with a quartz oscillator to compensate for phase noise. The digital frequency synthesis ensures precise control of the output frequency, avoiding the complexity of analog loop designs. Notably, ADFOD achieves a phase noise improvement of -35 dB compared to LC oscillator sources, offering higher stability and significantly reduced jitter. Implemented in 180 nm CMOS technology, the FoD achieves 130 fs jitter in sub-integer mode and 380 fs RMS jitter in fractional-N mode, with a power consumption of 28.8 mW. Meanwhile, the ADFOD, incorporating phase offset compensation and advanced digital frequency synthesis, reduces RMS jitter to below 1 ps with a power consumption of 56 mW. These results demonstrate the potential of fully digital frequency dividers for low-noise, high-precision clock generation. Keywords: Fractional Output Divider (FoD), All-Digital Fractional Output Divider (ADFOD), phase interpolation, sigma-delta modulator, digital frequency synthesis, phase offset compensation.