This thesis presents a novel Class-D audio amplifier designed and implemented using BCD C090D technology, a 90nm process node. This amplifier addresses the growing demand in the automotive sector for integrated devices capable of delivering high-quality audio performance. The proposed solution aims for extensive digitalization of the structure, seeking to shift as many blocks as possible in this direction. At the same time, it is based on analog feedback with the goal of reducing the converter’s requirements by working directly on the loop error signal. The amplifier features high reconfigurability, making it adaptable to various application scenarios. The obtained Class-D is capable of operating under typical conditions with a carrier frequency of 2.3 MHz, using an ADC that samples at only 4.6 MHz. Furthermore, a design technique is presented that highlights how the combined knowledge of analog and digital methodologies is essential nowadays to tackle challenges with an innovative approach. Finally, the measurement results performed on the chip are presented, carried out both in test modes dedicated to evaluating individual blocks and in functional mode. The sources of all identified limitations are located, and corresponding intervention solutions are proposed. The system exhibits a noise floor of 44 μVrms and a THD+N of 0.023% at 21mW.

Analysis, Design, and Characterization of a Class-D Audio Amplifier Integrating Analog and Digital Methodologies

STILGENBAUER, FRANCESCO
2026

Abstract

This thesis presents a novel Class-D audio amplifier designed and implemented using BCD C090D technology, a 90nm process node. This amplifier addresses the growing demand in the automotive sector for integrated devices capable of delivering high-quality audio performance. The proposed solution aims for extensive digitalization of the structure, seeking to shift as many blocks as possible in this direction. At the same time, it is based on analog feedback with the goal of reducing the converter’s requirements by working directly on the loop error signal. The amplifier features high reconfigurability, making it adaptable to various application scenarios. The obtained Class-D is capable of operating under typical conditions with a carrier frequency of 2.3 MHz, using an ADC that samples at only 4.6 MHz. Furthermore, a design technique is presented that highlights how the combined knowledge of analog and digital methodologies is essential nowadays to tackle challenges with an innovative approach. Finally, the measurement results performed on the chip are presented, carried out both in test modes dedicated to evaluating individual blocks and in functional mode. The sources of all identified limitations are located, and corresponding intervention solutions are proposed. The system exhibits a noise floor of 44 μVrms and a THD+N of 0.023% at 21mW.
27-feb-2026
Inglese
MALCOVATI, PIERO
Università degli studi di Pavia
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14242/358347
Il codice NBN di questa tesi è URN:NBN:IT:UNIPV-358347