This doctoral thesis, carried out in collaboration with TDK-InvenSense, presents the study and the design of an ultra-low power Analog-to-Digital Converter (ADC) suited for Audio Activity Detection (AAD) features. Exploiting oversampling and noise-shaping techniques, a Successive-Approximation-Register (SAR) converter is boosted to achieve high-resolution and low-noise while consuming the lowest possible power. AAD circuits are used in a wide variety of battery-operated devices, such as mobile phones and wearable devices, where the need to preserve energy is crucial. For this reason and many others that are explained later, power consumption is one of the main aspects considered. In this thesis are explained the working principles of a Quasi-Passive Error-Feedback Noise-Shaping SAR (QP-EF-NS-SAR) converter, from the conception to the measurements, passing through all the design steps that led to the final physical implementation. This converter reaches 78 dB of Dynamic Range (DR) achieving a Schreier Figure-of-Merit (FoMs) of 165.3 dB. Fabricated in a 65-nm BCD process, the proposed ADC core occupies 0.129 μm^2 consuming only 14.9 μW from a 1.2-V supply.
This doctoral thesis, carried out in collaboration with TDK-InvenSense, presents the study and the design of an ultra-low power Analog-to-Digital Converter (ADC) suited for Audio Activity Detection (AAD) features. Exploiting oversampling and noise-shaping techniques, a Successive-Approximation-Register (SAR) converter is boosted to achieve high-resolution and low-noise while consuming the lowest possible power. AAD circuits are used in a wide variety of battery-operated devices, such as mobile phones and wearable devices, where the need to preserve energy is crucial. For this reason and many others that are explained later, power consumption is one of the main aspects considered. In this thesis are explained the working principles of a Quasi-Passive Error-Feedback Noise-Shaping SAR (QP-EF-NS-SAR) converter, from the conception to the measurements, passing through all the design steps that led to the final physical implementation. This converter reaches 78 dB of Dynamic Range (DR) achieving a Schreier Figure-of-Merit (FoMs) of 165.3 dB. Fabricated in a 65-nm BCD process, the proposed ADC core occupies 0.129 μm^2 consuming only 14.9 μW from a 1.2-V supply.
Design of an Ultra-Low Power Quasi-Passive Error-Feedback Noise-Shaping SAR Converter for Audio Activity Detection
Tambussi, Marco
2026
Abstract
This doctoral thesis, carried out in collaboration with TDK-InvenSense, presents the study and the design of an ultra-low power Analog-to-Digital Converter (ADC) suited for Audio Activity Detection (AAD) features. Exploiting oversampling and noise-shaping techniques, a Successive-Approximation-Register (SAR) converter is boosted to achieve high-resolution and low-noise while consuming the lowest possible power. AAD circuits are used in a wide variety of battery-operated devices, such as mobile phones and wearable devices, where the need to preserve energy is crucial. For this reason and many others that are explained later, power consumption is one of the main aspects considered. In this thesis are explained the working principles of a Quasi-Passive Error-Feedback Noise-Shaping SAR (QP-EF-NS-SAR) converter, from the conception to the measurements, passing through all the design steps that led to the final physical implementation. This converter reaches 78 dB of Dynamic Range (DR) achieving a Schreier Figure-of-Merit (FoMs) of 165.3 dB. Fabricated in a 65-nm BCD process, the proposed ADC core occupies 0.129 μm^2 consuming only 14.9 μW from a 1.2-V supply.| File | Dimensione | Formato | |
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https://hdl.handle.net/20.500.14242/358494
URN:NBN:IT:UNIPV-358494