Design of integrated circuits for D band and E band receivers

This research focuses on the design, simulation, fabrication, and experimental validation of integrated circuits for D-band and E-band receiver front-ends, targeting 5G backhaul applications. With the rapid evolution of next-generation communication systems, the demand for ultra-high data rate and low latency mmWave links has accelerated the development of high-performance front-end components operating above 100 GHz. In this context, the work presented in this thesis aims to explore and optimize low-noise and high-gain receiver architectures implemented in SiGe BiCMOS technology, which offers an attractive trade-off between performance, cost, and integration capability compared to III-V semiconductor processes. The proposed receiver includes a two-stage cascode D-band LNA, a D-band to E-band down-conversion stage, an E-band tuned differential cascode LNA-VGA, and an I/Q Gilbert-cell mixer. The circuits were developed and verified using Cadence Virtuoso and EM co-simulation tools within the SiGe BiCMOS B55X process. The design methodology emphasizes accurate parasitic extraction, optimization for performance stability under variations, and bias network calibration to ensure reliable high-frequency operation. The LNA achieved a simulated gain of approximately 20 dB at 140 GHz and a noise figure around 8 dB, while maintaining acceptable linearity and input matching. This thesis presents the preliminary and the first tape-out iterations and, following the lessons learned from measurements on the preliminary prototype, where underestimation of parasitic elements caused downward frequency shift and gain degradation in measurements a redesign has been carried out. The new design integrates refined modeling and layout techniques that significantly improve consistency between simulation and measurement. Moreover, design trade-offs between inductive and resistive emitter degeneration in the Gilbert cell mixer were investigated, revealing the advantages of resistive degeneration for improved gain flatness at mmWave frequencies. The obtained results validate the feasibility of the proposed receiver front-end for 5G backhaul systems and contribute to the body of knowledge in mmWave circuit design, particularly in parasitic-aware modeling and bias optimization for SiGe BiCMOS technologies. The findings and methodologies presented here can serve as a foundation for future fully integrated transceiver systems and next-generation high-speed wireless links.