Analysis and Design of Voltage Mode Digital Doherty Power Amplifiers for Bluetooth Applications in 22nm CMOS Technology

This thesis analyzes the behavior of single supply N-way asymmetric Doherty power amplifiers, made of N Switched Capacitor Power Amplifiers (SCPAs) and a power combining network. The proposed analysis shows that, in the case of 2 combined SCPAs, there is an optimal power partition between them that maximizes the efficiency, at each output power level. The optimal control of the PA leads to two Power Back-Off (PBO) efficiency peaks, whose magnitude depends on the size of the switches of each SCPA, and on the matching network design. The optimization of both switch sizing and output network design is carried out analytically. The proposed analysis on the series combining transformer considers a generic number N of combined SCPAs. Adopting more than 2 cores allows to achieve higher output powers, with multiple efficiency peaks. A three-way digital Doherty amplifier designed to support all Bluetooth power classes (0, 4, 10, and 20 dBm) is simulated, in a 22nm CMOS technology. This amplifier integrates three SCPAs and adopts a novel design approach, referred to as ”dual-line-up”, which enables high efficiency at both high (20 dBm) and low (0 dBm) output powers, while operating with a single 0.7V supply. Specifically, the proposed architecture achieves three distinct efficiency peaks at 0 dB, 10 dB, and 19.3 dB PBO, corresponding to drain efficiencies of 47%, 47%, and 40%, respectively. To address the large footprint typically associated with series combining transformers (SCTs), a new matching network based on a transformer combined with a shunt inductor was developed. This network enables the realization of a single-ended asymmetric voltage-mode digital PA fabricated in a commercial 22 nm CMOS technology. The resulting prototype, implemented with a single 0.7 V supply, efficiently supports three Bluetooth power classes. It exhibits two efficiency peaks at 1.9 dBm and 10.5 dBm, achieving drain efficiencies of 37% and 41%, respectively. Furthermore, the output spectrum fully complies with the BLE spectral emission mask, confirming the suitability of the proposed solution for integrated BLE transmitters. Experimental measurements were also conducted at an operating frequency of 2.3 GHz to validate the theoretical analysis on optimal power partitioning. The measured results are in good agreement with theoretical predictions, further supporting the proposed design approach. A pseudo-differential version of the fabricated PA was subsequently designed in a 22 nm CMOS technology, employing a parallel combining transformer (PCT). Schematic-level simulations at 2.4 GHz indicate two efficiency peaks at 4.7 dBm and 13.2 dBm, with corresponding drain efficiencies of 38% and 48%. The use of pseudo-differential signaling, combined with a selective third-harmonic rejection filter, results in a cleaner output spectrum and higher simulated efficiency compared to the single-ended counterpart, while incurring only a minor increase in silicon area.