Analysis and Design of Galvanic Isolators for Gate Drivers with Full-Duplex Communication in HV CMOS Technology

In high‑performance power management systems, a clear separation between control and power domains is crucial to guarantee functional safety and reliable operation. Galvanic isolators play a key role in this context by preventing direct electrical connections while enabling secure and efficient communication across the isolation barrier. Traditionally, they serve as interfaces for the forward transmission of pulse‑width modulated (PWM) signals from the low‑voltage controller to the gate of the high‑power switch. However, increasingly stringent requirements on safety and reliability demand enhanced architectures, that also support control, monitoring and fault detection mechanisms. This calls for the implementation of high‑speed bidirectional communication links, enabling the backward transmission of real‑time status and feedback signals for monitoring and predictive maintenance. This thesis focuses on the analysis and design of fully‑integrated galvanic isolators for gate drivers, featuring asynchronous full‑duplex communication, targeting performance beyond the state of the art. Two implementations are proposed and fabricated in a 130 nm HV CMOS technology and their performance is evaluated through experimental characterization. The first solution deploys amplitude‑shift keying (ASK) and load‑shift keying (LSK) to simultaneously transmit bidirectional data over a single integrated transformer. A symmetric data rate of 66.7/66.7 Mb/s is demonstrated in a completely asynchronous communication scenario, without the need for a reference clock. The fabricated prototypes exhibit low power consumption and propagation delays below 20 ns. However, interactions between ASK and LSK modulation schemes introduce undesired jitter in the overall propagation delay, up to a maximum of 12 ns. To overcome these limitations, a second solution is designed. To minimize interactions between forward and backward signaling, ASK modulation is combined with frequency‑shift keying (FSK). The use of two modulation schemes that operate on (almost) orthogonal signal features allows for a significant reduction in the propagation delay jitter, which is measured to be below 4 ns, for ASK‑modulated forward data, and below 2.2 ns, for FSK‑modulated backward data. The overall propagation delay is less than 8 ns forward and 4 ns backward. Full‑duplex data transfer is achieved in a completely asynchronous communication scenario at the highest data rate of 100/167 Mb/s. Beyond these contributions, the thesis discusses potential extensions of the proposed architectures and explores the feasibility of wireless data transfer, laying the foundation for future research on high‑speed, low‑latency fully‑integrated isolation links.