ANALYSIS OF 4H-SIC CMOS DEVICES AND CIRCUITS

THIS PH.D. THESIS PRESENTS A COMPREHENSIVE ANALYSIS OF DEVICES AND BASIC ICS BUILDING BLOCKS FABRICATED IN 4H-SIC CMOS 2 ΜM FRAUNHOFER IISB’S TECHNOLOGY. THE ANALYSIS SPANS VERY HIGH TEMPERATURES, THAT IS, T=773K, TO CRYOGENIC TEMPERATURE, T=14K, AND IS SUPPORTED BY A MODELING ACTIVITY. AS A FIRST STEP, THE ELECTRICAL CHARACTERISTICS OF 4H-SIC LATERAL MOSFETS WITH CHANNEL LENGTHS OF L = 2ΜM AND 6ΜM ARE EVALUATED OVER A WIDE TEMPERATURE RANGE, I.E. FROM T=298K UP TO T=773K. MOSFETS CURRENT INCREASE WITH THE TEMPERATURE UP TO THE RANGE OF [523-623]K, AFTER WHICH IT DECREASES, THUS PREVENTING THERMAL RUN-AWAY. THIS BEHAVIOUR IS GIVEN BY THE COMBINED EFFECTS OF THRESHOLD VOLTAGE, VTH, AND FIELD EFFECT CHANNEL MOBILITY, ΜCH. IN ADDITION, PMOSFETS EXHIBIT A REVERSE SHORT CHANNEL EFFECT, AND THEIR FIELD EFFECT CHANNEL MOBILITY IS STRONGLY AFFECTED BY THE P-TYPE PARASITIC SERIES RESISTANCE. THE REPEATABILITY AND UNIFORMITY OF DEVICES AND CIRCUITS CHARACTERISTICS AMONG MULTIPLE THERMAL CYCLES STRENGTHENS THE RELIABILITY OF A HIGH TEMPERATURE CMOS TECHNOLOGY. A KEY FACTOR CONTRIBUTING TO THIS MATTER IS THE REDUCTION OF BORDER TRAPS IN THE GATE OXIDE. TO ADDRESS THIS, A POST-PROCESSING ANNEALING STEP AT 673 K IS PROPOSED. REGARDLESS OF THE ANNEALING ENVIRONMENT, I.E. AMBIENT, VACUUM AND NITROGEN, IMPROVEMENTS IN TERMS OF REPEATABILITY DURING DIFFERENT TEMPERATURE AND UNIFORMITY AMONG DIES OF ELECTRICAL CHARACTERISTICS ARE OBTAINED. MOREOVER, THE PROCESS INDEPENDENCE FROM AMBIENT CONDITIONS MAKES IT SUITABLE AS A FINAL STEP IN CMOS FABRICATION. AT CRYOGENIC TEMPERATURE, ESPECIALLY IN AEROSPACE APPLICATIONS, THE INCOMPLETE DOPANT IONIZATION CAN BE CRUCIAL FOR 4H-SIC CMOS DEVICES. A LATERAL P^+-P-N^+ DIODE IS INVESTIGATED DOWN TO 175K, REVEALING A STRONG REDUCTION OF THE I-V CHARACTERISTIC IN LINEAR REGION. THIS BEHAVIOUR IS ATTRIBUTED TO A COMBINATION OF A TRAP IN THE INTRINSIC P-TYPE REGION AND A LIMITATION OHMIC CONTACT MECHANISM. TO FURTHER INVESTIGATE THE IMPACT OF AL^+-IMPLANTED REGIONS ON DEVICE PERFORMANCE AT CRYOGENIC TEMPERATURES, A REFERENCE STRUCTURE CONSISTING OF A VERTICAL AL^+ ANODE IMPLANTED 4H-SIC P-I-N DIODE IS STUDIED AT TEMPERATURES BELOW 80 K. A HOLE TRAP LOCATED 375 MEV ABOVE THE VALENCE BAND IS IDENTIFIED AS THE CAUSE OF THE NEGATIVE RESISTANCE BEHAVIOUR OF THE ANALYSED DIODE. AS PART OF THE ANALYSIS OF MOSFET PERFORMANCE AT CRYOGENIC TEMPERATURE, I.E. DOWN TO T = 14 K, DIODE-CONNECTED NMOSFETS AND PMOSFETS ARE EXAMINED FOR THEIR POTENTIAL USE AS TEMPERATURE SENSORS. THE HIGH DENSITY OF INTERFACE STATES AT THE SIO_2/4H-SIC INTERFACE LEADS TO A COMPLEX TEMPERATURE DEPENDENCE OF THE VGS-T CHARACTERISTIC. MULTIPLE TEMPERATURE RANGES ARE SELECTED TO IMPROVE SENSOR LINEARITY. THE BEST RESULTS ARE OBTAINED WITH NMOSFET-BASED SENSORS OPERATING IN THE SUBTHRESHOLD REGION AT T < 200 K AND IDS< 1.59 ΜA. FURTHER IMPROVEMENTS IN LINEARITY, R^2 = 0.9979, AND TEMPERATURE RANGE, 100K < T < 481K, ARE ACHIEVED USING A COMPLEMENTARY TO ABSOLUTE TEMPERATURE, CTAT, NMOSFETS BASED CONFIGURATION.THE DESIGN OF INTEGRATED CIRCUITS REQUIRES COMPACT AND ACCURATE DEVICE MODELS. DUE TO THE INCOMPLETE UNDERSTANDING OF 4H-SIC LATERAL MOSFET BEHAVIOUR, FEW CMOS COMPACT MODELS EXIST. A SPICE LEVEL 3-BASED COMPACT DC MODEL IS DEVELOPED FOR BOTH NMOSFETS AND PMOSFETS, ACCOUNTING FOR VARIOUS BIASING CONDITIONS AND TEMPERATURE RANGES. THE MODEL INCORPORATES GEOMETRY DEPENDENCIES AND BODY EFFECTS THROUGH A SEMI-EMPIRICAL VTH FORMULATION. EXPERIMENTAL VALIDATION IS CARRIED OUT USING BOTH INDIVIDUAL DEVICES, AND INTEGRATED CMOS CIRCUITS, INCLUDING NOT GATE, CASCODE CURRENT MIRROR, AND VOLTAGE SCHMITT TRIGGER. COMPARISONS WITH HIGHER-ORDER MODELS DEMONSTRATE THAT THE PROPOSED MODEL ACHIEVES A GOOD BALANCE BETWEEN COMPLEXITY AND ACCURACY, OFTEN OUTPERFORMING MORE COMPLEX MODELS IN PRACTICAL SIMULATION SCENARIOS.