Design and testing of CMOS radiation detectors for High Energy Physics Experiments

In recent years, the study and the development of novel architectures and tech- nologies to improve performance of silicon pixel detectors became a pivotal node for High Energy Physics (HEP) experiments. Their extremely tight constraints of spatial resolution, low power dissipation, speed, granularity, signal-to-noise ratio and radiation hardness, led the scientific community to continuously research new solutions to satisfy newer and more stringent requirements. In this context, the two main categories of detectors technologies have been represented by Hybrid Pixel Detectors (HPDs) and Monolithic Active Pixel Sensors (MAPS). Traditionally, HPDs constitute the more widespread technology for particle pixel detectors: due to their excellent characteristics, they are adopted for the inner layers of the most of current main HEP experiments. However, on the other side, the relatively novel monolithic sensors technology became recently more and more interesting as leading replacing technology due to its improved radiation hardness and the lower material budget and cost with respect to HPDs. In this thesis an introduction to these technologies will be carried out and some related research results will be shown. In Chapter 1 Hybrid Pixel Detectors technology will be described, with an additional part dedicated to some literature examples about HEP experiments which adopted this kind of sensors for their inner layers. This chapter acts as an introduction to the CHIPIX65 (CHIp for PIXel detector in a 65 nm process) prototype shown in Chapter 3 and to the Phase-Locked Loop described in Chapter 5.In Chapter 2 MAPS (Monolithic Active Pixel Sensors) technology will be intro- duced, from the early prototypes based on 3-T and 4-T architecture until the last examples of monolithic sensors implemented inside more recent particle detectors upgrades. This part is preparatory to Chapter 5, where the MATISSE prototype is described both to the development and to the testing point of view. Chapter 3 is dedicated to CHIPIX65 project and the development of a novel prototype of an 65 nm CMOS HPD: realized in collaboration of some INFN Italian groups, this is the first example of HPD fully developed in a sub-micron CMOS technology. Starting with a short introduction to architecture and readout modes, this chapter shows some important testing results presented in Strasbourg during an IEEE MIC-NSS Conference talk in 2016. Chapter 4 is fully dedicated to a low-noise and compact Phase-Locked Loop (PLL) built in the same 65 nm CMOS technology. After some theoretical and introductory sections, the prototype will be described and test results provided. Chapter 5 is fully dedicated to the development and test of a prototype of MAPS, called MATISSE (Monolithic AcTIve pixel SenSor Electronics). Developed by INFN groups of Turin and Padua, University of Trento and TIFPA, it is an example of a fully-depleted monolithic active sensor. Here, some sensor and readout electronics will be described, followed by some tests. These results have been presented during a poster session in Atlanta during the IEEE MIC-NSS Conference in 2017. Appendices will cover some follow-up topics related to the previous sections. Appendix A summarizes radiation effects on silicon devices, both total dose and heavy-ions effect: this section is useful to referring to all the parts related to radiation hardness tests of described prototypes. Appendix B outlines some practical guidelines about Process Design Kit (PDK) of a given technology process. Indeed, before starting the design of any ASIC device, a PDK needs to be provided by the foundry, installed and configured in order to allow to work with. Appendix C is dedicated to some theoretical issues on oscillator phase noise, which represent a huge subject in Phase-Lock Loop theory; however, since it is not covered by the analysis and tests on the PLL prototype, it has been chosen to put this part separately to Chapter 4.