CMOS Continuous-Time Linear Equalizers for High-Speed Serial Links

The explosive growth of internet traffic, driven by multimedia, Internet of Things and cloud services, continuously pushes for higher bandwidth and aggressive scaling of I/Os for high-speed electrical links. Recent standards require transceivers working at 25~28Gb/s with NRZ (non-return-to-zero) modulation or 50~56Gb/s with PAM-4 (Pulse-amplitude-modulation-4) modulation. Channel impairments degrade the signal integrity significantly for transceivers working at such high data rate. To ensure link reliability, equalization is necessary for compensating channel impairments. Moreover, to achieve a target BER (bit-error-rate) with lower power consumption, accurate and energy-efficient equalization techniques have been exploited in recent transceivers design. In receiver design, continuous-time-linear-equalizer (CTLE) shows its advantages for its low power consumption. This Ph.D. work has been focused on the study of analog equalization techniques and presents three different designs tailored to 25Gb/s NRZ, 56Gb/s PAM-4 and 112Gb/s PAM-4 respectively. First, a novel CTLE based on transversal architecture is presented. Thanks to the transversal architecture, it shows high accuracy to compensate inter-symbol interference (ISI) and flexibility to accommodate variable speed and channel profiles. The CTLE was realized in 28nm FD SOI technology and measurements are presented at data rate from 5Gb/s to 25Gb/s across 20dB-loss channels. Core power dissipation is 17mW from 1V supply and horizontal eye opening at BER=10-12 is larger than 50%, comparing favorably against previously reported equalizers targeting similar data-rate and channel loss. Recently, to satisfy the higher bandwidth demand, transceivers working at 50~56Gb/s per lane have been proposed. Since the impairments of channels used for 25-28Gb/s NRZ by increasing bandwidth significantly limit serial link data rate, a double bandwidth efficiency modulation PAM-4 is proposed to increase the data rate. In this dissertation, a fully analog PAM-4 receiver working up to 64Gb/s is presented. Receiver equalization relies on a flexible CTLE that can be optimally adapted at low, mid and high frequency independently, providing a very accurate inversion of channel transfer function. The CTLE meets the performance requirements of the CEI-56G-VSR standard without requiring DFE (decision-feedback-equalizer) implementation. The test chip is implemented in 28nm FD SOI technology, at the maximum speed, the receiver draws 180mA from 1V supply, corresponding to 2.8mW/Gb/s only. Electrical interfaces used with 100Gb/s singling are being investigated to satisfy the continual growth of bandwidth demand. In the newer Ethernet standard, IEEE 802.3ck, one-single lane 100Gb/s interfaces are specified. In this thesis, a 112Gb/s PAM-4 analog front-end designed in 7nm FinFet technology is presented. The target is to be merged with an analog-to-digital converter (ADC) based receiver so as to take advantage of high-performance digital signal processing (DSP) in 7nm FinFet technology. However, significant changes in transistor behavior, scaled supply voltage, and very different layout rules result in challenges in analog circuits design. Design considerations regarding linearity and bandwidth of analog circuits in 7nm FinFet technology are presented in this thesis. Simulation results prove the analog front-end can successfully recover 112Gb/s PAM-4 sequences transmitted through a 15dB Synectic channel.