Dual-Mode Precise Bias Circuit and a Low-Noise and Wideband AFE for Fly-Height Sensors in Hard Disk Drives

This thesis reports the system-level discussion, simulation design, and fabrication results of a novel analog ASIC fabricated in 130nm BiCMOS technology and used for interfacing resistive thermal sensors known as Fly Height Sensors (FHSs) attached to the magnetic recording heads in modern hard-disk-drives (HDDs) to measure the resistance variation of the sensor and control the fly height of the read/write head. The magnitude of the sensor signal serves as a measure of the proximity between the head and the media known as “fly height” which must accurately be controlled to increase the storage capacity of HDDs. The proposed interface includes two parts; (1) a dual-mode precise bias circuit which accurately applies a differential bias with a programmable common mode voltage across the FHS in both the voltage (V) and current (I) modes without requiring any calibrations while featuring fast and smooth transient response, (2) front-end amplifiers creating two separate signal paths with low and high frequency responses, called LF and HF blocks, utilized for controlling the fly height and mapping the roughness of the disk surface respectively. The proposed bias circuit demonstrates high-impedance loading behavior on the sensor terminals in both V- and I-mode to have a unity signal gain at the sensor port and deliver it to the front-end amplifiers, resulting an improvement of the overall noise performance of the interface. Thanks to utilizing a noise cancellation technique, the bias noise at the output of the LF block is suppressed, leading to one order of magnitude noise power attenuation. An area- and power-efficient, low-noise, and wide bandwidth front-end proposed for the HF block implementation, featuring a low cut-off frequency without requiring a configurable bias loop. Degenerated differential pair with resistive loads, split tail currents, and Caprio’s quad offering low gain variation over the temperature and process implemented as the front-end gain stages. The fabricated chip features an active area of 1.28 mm2 with a power consumption in the range of 110 to 172 mW for the V-mode and 78 to 107 mW for the I-mode, considering typical supply voltages of +3.3V and -2.6V, and depending on the sensor resistance (RSNS) and the bias condition (ISNS).