Analysis and Design of High-Performance Low-Power IoT Transmitters, and Ultra-Low-Noise Millimetre-Wave Oscillators in CMOS Technology

Integrated electronics are the backbone of the technological progress we enjoy every day. Without chips, there would be no modern telecommunications or computing, no internet, computers, smartphones, AI and so on. The whole world is more dependent than ever on the successful development of newer, faster and more efficient electronic circuits, especially in the radio frequency (RF) segment. The focus of this work is twofold: on the one hand, the exponential increase in the number of connected devices is driving the development of increasingly complex, efficient and cheap low-power front-ends; on the other hand, the introduction of faster communication protocols, such as 6G, the rise of automotive RADARs, calls for the development of high-performance, low-noise integrated oscillators. After a brief introduction, the first part of the thesis focuses on the design of a low power, efficient 2.4 GHz Cartesian transmitter for Internet-of-Things (IoT) applications. Firstly, a thorough analysis of the passive resistive mixer is carried out, showing how its operation leads to inefficient transmitters. A passive reactive mixer is proposed as a solution to the shortcomings of the common passive resistive mixer. The proposed mixer is analysed and a set of useful design equations is obtained. The prototypes of the IoT Cartesian transmitter are realised in a 22 nm FD-SOI process and show an efficiency of 22% for a 16-QAM 2.4 Mbaud signal with an average output power of 2.7 dBm. The second part of the thesis focuses on the design of low phase noise oscillators. Achieving ultra-low phase noise in ultra-scaled CMOS technologies is no easy task due to low supply voltages and low quality of the passive devices. Three different topologies are designs are proposed as an alternative solution. First, a reconfigurable octacore DCO exploits the synchronisation of the oscillators to improve the phase noise by 9 dB; the reconfigurable network allows to dynamically trade phase noise with power consumption. The impact of the switches on the phase noise and coupling bandwidth is evaluated using a rigorous time-variant analysis. The prototypes are realised in a 28 nm CMOS process, and show a phase noise of -126 dBc/Hz at 1 MHz offset at 10.7 GHz. Secondly, a series CMOS VCO with a transformer based feedback network is presented: series VCO are able to achieve much better phase noise by a factor of 20logQ where Q is the quality factor of the tank. Finally, a 5 GHz VCO with a stacked differential-pair is presented. The stacking of the active devices allow the VCO to operate from a 1.6 V supply without reliability concerns. The prototypes, realised in a 22 nm FD-SOI CMOS technology and achieve a phase noise of -126 dBc/Hz at 1 MHz offset at 5.2 GHz and a tuning range of 16.6%.